The present invention relates to a method of testing a semiconductor apparatus.
In the method of testing the semiconductor apparatus, a signal delay in a predetermined critical path is measured in order to guarantee a speed performance. The critical path is a path, of signal paths of logic circuits, configured in such manner that an erroneous operation is generated when a signal is not transmitted within a defined time length.
As the semiconductor apparatus is more and more miniaturized, variation is generated in process parameters for each region in the same semiconductor apparatus. Further, delay time is accordingly variable. As a result, a path having an increased delay time in a signal transmission than an initially assumed critical path is generated, resulting in a failure to guarantee a predetermined operation speed.